A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL Using Aperture Phase Detector-Based DLL Windowing Technique

This paper proposes a self-aligned sub-harmonically injection locked phase loop (SILPLL) in 180-nm Semi Conductor Laboratory (SCL) CMOS technology. In this work, an aperture detector (APD) based delay (DLL) with windowing technique is proposed to dynamically align the timing of pulse rising edge voltage controlled oscillator. contrast classical SILPLL, work replaces commonly deployed tri-state frequency (PFD) DLL by APD, which becomes active over pulse-window. The APD reduces in-band noise due charge pump 12 dBc at 200 KHz offset comparison DLL. A detailed mathematical model sources presented for architecture. Additionally, includes analysis effect different design aspects such as locking range, and realignment factor. architecture operates 1.8 GHz output frequency, simulated −120.6 dBc/Hz 1 MHz integrated root-mean-square jitter 0.96 ps from 10 kHz 30 MHz. implemented PLL consumes 6.6 mW V power supply.